VHDL數(shù)字系統(tǒng)設(shè)計(jì)：英文版

Preface                  
      1 Introduttion                  
      1.1 Modern digital design                  
      1.2 CMOS technology                  
      1.3 Programmable logic                  
      1.4 Electrical propenies                  
      1.5 Summary                  
      1.6 Funher reading                  
      Exercises                  
      2 Combinational logic design                  
      2.1 Boolean algebra                  
      2.2 Logic gates                  
      2.3 Combinational logic design                  
      2.4 Timing                  
      2.5 Number codes                  
      2.6 Summary                  
      2.7 Funher reading                  
      Exercises                  
      3 Combinational logic using VHDL gate models                  
      3.1 Entities and architectures                  
      3.2 Identifiers, spaces and commenb                  
      3.3 Netlists                  
      3.4 Signal assignments                  
      3.5 Generics                  
      3.6 Constant and open pons                  
      3.7 Testbenches                  
      3.8 Configurations                   
      3.9 Summary                  
      3.10 Funher reading                  
      Exercises                  
      4 Combinatlonal building blocks                  
      4.1 Three-state buffers                  
      4.2 Decoders                  
      4.3 Multiplexers                  
      4.4 Priority encoder                  
      4.5 Adders                  
      4.6 Parity checker                  
      4.7 Summary                  
      4.8 Further reading                  
      Exercises                  
      5 Synchronous sequential design                  
      5.1 Synchronous sequential systems                  
      5.2 Models of synchronous sequential systems                  
      5.3 Algorithmic state machines                  
      5.4 Synthesis from ASM charts                  
      5.5 5tate machines in VHDL                  
      5.6 Summary                  
      5.7 Funher reading                  
      Exercises                  
      6 VHDL models of sequentlal logic blocks                  
      6.1 Latches                  
      6.2 Flip-fiops                  
      6.3 JK and T flip-flops                  
      6.4 Registers and shift registers                  
      6.5 Counters                  
      6.6 Memory                  
      6.7 Sequential multiplier                  
      6.8 Summary                  
      6.9 Funher reading                  
      Exercises                  
      7 Complex sequential systems                  
      7.1 Linked state machines                  
      7.2 Datapath/controller panitioning                  
      7.3 Instructions                  
      7.4 A simple microprocessor                  
      7.5 VHDL model of a simple microprocessor                  
      7.6 Summary                  
      7.7 Futher reading                  
      Exercises                  
      8 VHDL simulation                  
      8.1 Event-driven simulation                  
      8.2 Simulation of VHDL models                  
      8.3 Simulation modelling issues                  
      8.4 Fike operations                  
      8.5 Summary                  
      8.6 Funher reading                  
      Exercises                  
      9 VHDL synthesls                  
      9.1 RTL synthesis                  
      9.2 Constraints                  
      9.3 Synthesis for FPCAs                  
      9.4 Behavioural synthesis                  
      9.5 Summary                  
      9.6 Futher reading                  
      Exercises                  
      10 Testing digital systems                  
      1O.1 The need for testing                  
      10.2 Fault models                  
      10.3 Fault-oriented test pattern generation                  
      10.t Fault simulation                  
      10.5 Fault simulation in VHDL                  
      10.6 Summary                  
      10.7 Further reading                  
      Exercises                  
      11 Design for testability                  
      11.1 Ad hoc testability improvements                  
      11.2 Structured design for test                  
      11.3 Built-in self-test                  
      11.4 Boundary scan (IEEE 1149.1)                  
      11.5 Summary                  
      11.6 Further reading                  
      Exercises                  
      12 Asynthronous sequential design                  
      12.1 Asynchronous circuib                  
      12.2 Analysis of asynchronous circuits                  
      12.3 Design of asynchronous sequential circuits                  
      12.4 Setup and hold times and metastability                  
      12.5 Summary                  
      12.6 Further reading                  
      Exercises                  
      Appendices                  
      A VHDL standards                  
      B Verilog                  
      C 1076A - shared variables                  
      Bibliography                  
      Answers to selected problems                  
      Index