Preface Acknowledgments Introduction 1 Test and Design-for-Test Fundamentals 1.1 Introduction to Test and DFT Fundamentals 1.1.1 Purpose 1.1.2 Introduction to Test, the Test Process, and Design-for-Test 1.1.3 Concurrent Test Engineering 1.2 The Reasons for Testing 1.2.1 Why Test? Why Add Test Logic? 1.2.2 Pro and Con Perceptions of DFT 1.3 The Definition of Testing 1.3.1 What Is Testing? 1.3.2 Stimulus 1.3.3 Response 1.4 Test Measurement Criteria 1.4.1 What Is Measured? 1.4.2 Fault Metric Mathematics 1.5 Fault Modeling 1.5.1 Physical Defects 1.5.2 Fault Modeling 1.6 Types of Testing 1.6.1 Functional Testing 1.6.2 Structural Testing 1.6.3 Combinational Exhaustive and Pseudo-Exhaustive Testing 1.6.4 Full Exhaustive Testing 1.6.5 Test Styles 1.7 Manufacturing Test 1.7.1 The Manufacturing Test Process 1.7.2 Manufacturing Test Load Board 1.7.3 Manufacturing Test Program 1.8 Using Automatic Test Equipment 1.8.1 Automatic Test Equipment 1.8.2 ATE Limitations 1.8.3 ATE Cost Considerations 1.9 Test and Pin Timing 1.9.1 Tester and Device Pin Timing 1.9.2 Tester Edge Sets 1.9.3 Tester Precision and Accuracy 1.10 Manufacturing Test Program Components 1.10.1 The Pieces and Parts of a Test Program 1.10.2 Test Program Optimization 1.11 Recommended Reading 2 Automatic Test Pattern Generation Fundamentals 2.1 Introduction to Automatic Test Pattern Generation 2.1.1 Purpose 2.1.2 Introduction to Automated Test Pattern Generation 2.1.3 The Vector Generation Process Flow 2.2 The Reasons for ATPG 2.2.1 Why ATPG? 2.2.2 Pro and Con Perceptions of ATPG 2.3 The Automatic Test Pattern Generation Process 2.3.1 Introduction to ATPG 2.4 Introducing the Combinational Stuck-At Fault 2.4.1 Combinational Stuck-At Faults 2.4.2 Combinational Stuck-At Fault Detection 2.5 Introducing the Delay Fault 2.5.1 Delay Faults 2.5.2 Delay Fault Detection 2.6 Introducing the Current-Based Fault 2.6.1 Current-Based Testing 2.6.2 Current-Based Testing Detection 2.7 Testability and Fault Analysis Methods 2.7.1 Why Conduct ATPG Analysis or Testability Analysis? 2.7.2 What Types of Testability Analysis Are Available? 2.7.3 Fault Effective Circuits 2.7.4 Controllability-Observability Analysis 2.7.5 Circuit Learning 2.8 Fault Masking 2.8.1 Causes and Effects of Fault Masking 2.8.2 Fault Masking on Various Fault Models 2.9 Stuck Fault Equivalence 2.9.1 Fault Equivalence Optimization 2.9.2 Fault Equivalence Side Effects 2.10 Stuck-At ATPG 2.10.1 Fault Selection 2.10.2 Exercising the Fault 2.10.3 Detect Path Sensitization 2.11 Transition Delay Fault ATPG 2.11.1 Using ATPG with Transition Delay Faults 2.11.2 Transition Delay Is a Gross Delay Fault 2.12 Path Delay Fault ATPG 2.12.1 Path Delay ATPG 2.12.2 Robust Fault Detection 2.12.3 The Path Delay Design Description 2.12.4 Path Enumeration 2.13 Current-Based Fault ATPG 2.13.1 Current-Based ATPG Algorithms 2.14 Combinational versus Sequential ATPG 2.14.1 Multiple Cycle Sequential Test Pattern Generation 2.14.2 Multiple Time Frame Combinational ATPG 2.14.3 Two-Time-Frame ATPG Limitations 2.14.4 Cycle-Based ATPG Limitations 2.15 Vector Simulation 2.15.1 Fault Simulation 2.15.2 Simulation for Manufacturing Test 2.16 ATPG Vectors 2.16.1 Vector Formats 2.16.2 Vector Compaction and Compression 2.17 ATPG-Based Design Rules 2.17.1 The ATPG Tool "NO" Rules List 2.17.2 Exceptions to the Rules 2.18 Selecting an ATPG Tool 2.18.1 The Measurables 2.18.2 The ATPG Benchmark Process 2.19 ATPG Fundamentals Summary 2.19.1 Establishing an ATPG Methodology 2.20 Recommended Reading 3 Scan Architectures and Techniques 3.1 Introduction to Scan-Based Testing 3.1.1 Purpose 3.1.2 The Testing Problem 3.1.3 Scan Testing 3.1.4 Scan Testing Misconceptions 3.2 Functional Testing 3.3 The Scan Effective Circuit 3.4 The Mux-D Style Scan Flip-Flops 3.4.1 The Multiplexed-D Flip-Flop Scan Cell 3.4.2 Perceived Silicon Impact of the Mux-D Scan Flip-Flop 3.4.3 Other Types of Scan Flip-Flops 3.4.4 Mixing Scan Styles 3.5 Preferred Mux-D Scan Flip-Flops 3.5.1 Operation Priority of the Multiplexed-D Flip-Flop Scan Cell 3.5.2 The Mux-D Flip-Flop Family 3.6 The Scan Shift Register or Scan Chain 3.6.1 The Scan Architecture for Test 3.6.2 The Scan Shift Register (a.k.a The Scan Chain) 3.7 Scan Cell Operations 3.7.1 Scan Cell Transfer Functions 3.8 Scan Test Sequencing 3.9 Scan Test Timing 3.10 Safe Scan Shifting 3.11 Safe Scan Sampling: Contention-Free Vectors 3.11.1 Contention-Free Vectors 3.12 Partial Scan 3.12.1 Scan Testing with Partial-Scan 3.12.2 Sequential ATPG 3.13 Multiple Scan Chains 3.13.1 Advantages of Multiple Scan Chains 3.13.2 Balanced Scan Chains 3.14 The Borrowed Scan Interface 3.14.1 Setting up a Borrowed Scan Interface 3.14.2 The Shared Scan Input Interface 3.14.3 The Shared Scan Output Interface 3.15 Clocking, On-Chip Clock Sources, and Scan 3.15.1 On-Chip Clock Sources and Scan Testing 3.15.2 On-Chip Clocks and Being Scan Tested 3.16 Scan-Based Design Rules 3.16.1 Scan-Based DFT and Design Rules 3.16.2 The Rules 3.17 Stuck-At (DC) Scan Insertion 3.17.1 DC Scan Insertion 3.17.2 Extras 3.17.3 DC Scan Insertion and Multiple Clock Domains 3.18 Stuck-At Scan Diagnostics 3.18.1 Implementing Stuck-At Scan Diagnostics 3.18.2 Diagnostic Fault Simulation 3.18.3 Functional Scan-Out 3.19 At-Speed Scan (AC) Test Goals 3.19.1 AC Test Goals 3.19.2 Cost Drivers 3.20 At-Speed Scan Testing 3.20.1 Uses of At-Speed Scan Testing 3.20.2 At-Speed Scan Sequence 3.20.3 At-Speed Scan versus DC Scan 3.21 The At-Speed Scan Architecture 3.21.1 At-Speed Scan Interface 3.21.2 At-Speed "Safe Shifting" Logic 3.21.3 At-Speed Scan Sample Architecture 3.22 The At-Speed Scan Interface 3.22.1 At-Speed Scan Shift Interface 3.22.2 At-Speed Scan Sample Interface 3.23 Multiple Clock and Scan Domain Operation 3.23.1 Multiple Timing Domains 3.24 Scan Insertion and Clock Skew 3.24.1 Multiple Clock Domains, Clock Skew, and Scan Insertion 3.24.2 Multiple Time Domain Scan Insertion 3.25 Scan Insertion for At-Speed Scan 3.25.1 Scan Cell Substitution 3.25.2 Scan Control Signal Insertion 3.25.3 Scan Interface Insertion 3.25.4 Other Considerations 3.26 Critical Paths for At-Speed Scan 3.26.1 Critical Paths 3.26.2 Critical Path Selection 3.26.3 Path Filtering 3.26.4 False Path Content 3.26.5 Real Critical Paths 3.26.6 Critical Path Scan-Based Diagnostics 3.27 Scan-Based Logic BIST 3.27.1 Pseudo-Random Pattern Generation 3.27.2 Signature Analysis 3.27.3 Logic Built-In Self-Test 3.27.4 LFSR Science (A Quick Tutorial) 3.27.5 X-Management 3.27.6 Aliasing 3.28 Scan Test Fundamentals Summary 3.29 Recommended Reading 4 Memory Test Architectures and Techniques 4. 1 Introduction to Memory Testing 4.1.1 Purpose 4.1.2 Introduction to Memory Test 4.2 Types of Memories 4.2.1 Categorizing Memory Types 4.3 Memory Organization 4.3.1 Types of Memory Organization 4.4 Memory Design Concerns 4.4.1 Trade-Offs in Memory Design 4.5 Memory Integration Concerns 4.5.1 Key Issues in Memory Integration 4.6 Embedded Memory Testing Methods 4.6.1 Memory Test Methods and Options 4.7 The Basic Memory Testing Model 4.7.1 Memory Testing 4.7.2 Memory Test Fault Model 4.7.3 Memory Test Failure Modes 4.8 The Stuck-At Bit-Cell Based Fault Models 4.8.1 Stuck-At Based Memory Bit-Cell Fault Models 4.8.2 Stuck-At Fault Exercising and Detection 4.9 The Bridging Defect-Based Fault Models 4.9.1 Bridging Defect-Based Memory Test Fault Models 4.9.2 Linking Defect Memory Test Fault Models 4.9.3 Bridging Fault Exercising and Detection 4.10 The Decode Fault Model 4.10.1 Memory Decode Fault Models 4.10.2 Decode Fault Exercising and Detection 4.11 The Data Retention Fault 4.11.1 Memory Test Data Retention Fault Models 4.11.2 DRAM Refresh Requirements 4.12 Diagnostic Bit Mapping 4.12.1 Memory Test Diagnostics: Bit Mapping 4.13 Algorithmic Test Generation 4.13.1 Introduction to Algorithmic Test Generation 4.13.2 Automatic Test Generation 4.13.3 BIST-Based Algorithmic Testing 4.14 Memory Interaction with Scan Testing 4.14.1 Scan Test Considerations 4.14.2 Memory Interaction Methods 4.14.3 Input Observation 4.14.4 Output Control 4.15 Scan Test Memory Modeling 4.15.1 Modeling the Memory for ATPG Purposes 4.15.2 Limitations 4.16 Scan Test Memory Black-Boxing 4.16.1 The Memory Black-Boxing Technique 4.16.2 Limitations and Concerns 4.17 Scan Test Memory Transparency 4.17.1 The Memory Transparency Technique 4.17.2 Limitations and Concerns 4.18 Scan Test Memory Model of The Fake Word 4.18.1 The Fake Word Technique 4.18.2 Limitations and Concerns 4.19 Memory Test Requirements for MBIST 4.19.1 Memory Test Organization 4.20 Memory Built-In Self-Test Requirements 4.20.1 Overview of Memory BIST Requirements 4.20.2 At-Speed Operation 4.21 An Example Memory BIST 4.21.1 A Memory Built-In Self-Test 4.21.2 Optional Operations 4.21.3 An Example Memory Built-In Self-Test 4.22 MBIST Chip Integration Issues 4.22.1 Integrating Memory BIST 4.23 MBIST Integration Concerns 4.23.1 MBIST Default Operation 4.24 MBIST Power Concerns 4.24.1 Banked Operation 4.25 MBIST Design-Using LFSRs 4.25.1 Pseudo-Random Pattern Generation for Memory Testing 4.25.2 Signature Analysis and Memory Testing 4.25.3 Signature Analysis and Diagnostics 4.26 Shift-Based Memory BIST 4.26.1 Shift-Based Memory Testing 4.26.2 Output Assessment 4.27 ROM BIST 4.27.1 Purpose and Function of ROM BIST 4.27.2 The ROM BIST Algorithm 4.27.3 ROM MISR Selection 4.27.4 Signature Compare Method 4.28 Memory Test Summary 4.29 Recommended Reading 5 Embedded Core Test Fundamentals 5.1 Introduction to Embedded Core Testing 5.1.1 Purpose 5.1.2 Introduction to Embedded Core-Based Chip Testing 5.1.3 Reuse Cores 5.1.4 Chip Assembly Using Reuse Cores 5.2 What Is a Core? 5.2.1 Defining Cores 5.2.2 The Core DFT and Test Problem 5.2.3 Built-In DFT 5.3 What is Core-Based Design? 5.3.1 Design of a Core-Based Chip 5.3.2 Core-Based Design Fundamentals 5.4 Reuse Core Deliverables 5.4.1 Embedded Core Deliverables 5.5 Core DFT Issues 5.5.1 Embedded Core-Based Design Test Issues 5.6 Development of a ReUsable Core 5.6.1 Embedded Core Considerations for DFT 5.7 DFT Interface Considerations---Test Signals 5.7.1 Embedded Core Interface Considerations for DFT--Test Signals 5.8 Core DFT Interface Concerns--Test Access 5.8.1 Test Access to the Core Interface 5.9 DFT Interface Concerns--Test Wrappers 5.9.1 The Test Wrapper as a Signal reduction Element 5.9.2 The Test Wrapper as a Frequency Interface 5.9.3 The Test Wrapper as a Virtual Test Socket 5.10 The Registered Isolation Test Wrapper 5.11 The Slice Isolation Test Wrapper 5.12 The Isolation Test Wrapper--Slice Cell 5.13 The Isolation Test Wrapper--Core DFT Interface 5.14 Core Test Mode Default Values 5.14.1 Internal versus External Test Quiescence Defaults Application 5.15 DFT Interface Wrapper Concerns 5.15.1 Lack of Bidirectional Signals 5.15.2 Test Clock Source Considerations 5.16 DFT Interface Concerns--Test Frequency 5.16.1 Embedded Core Interface Concerns for DFT--Test Frequency 5.16.2 Solving the Frequency Problem 5.17 Core DFT Development 5.17.1 Internal Parallel Scan 5.17.2 Wrapper Parallel Scan 5.17.3 Embedded Memory BIST 5.17.4 Other DFT Features 5.18 Core Test Economics 5.18.1 Core DFT, Vectors, and Test Economics 5.18.2 Core Selection with Consideration to DFT Economics 5.19 Chip Design with a Core 5.19.1 Elements of a Core-Based Chip 5.19.2 Embedded Core Integration Concerns 5.19.3 Chip-Level DFT 5.20 Scan Testing the Isolated Core 5.21 Scan Testing the Non-Core Logic 5.21.1 Scan Testing the Non-Core Logic in Isolation 5.21.2 Chip-Level Testing and Tester Edge Sets 5.22 User Defined Logic Chip-Level DFT Concerns 5.23 Memory Testing with BIST 5.24 Chip-Level DFT Integration Requirements 5.24.1 Embedded Core-Based DFT Integration Architecture 5.24.2 Physical Concerns 5.25 Embedded Test Programs 5.26 Selecting or Receiving a Core 5.27 Embedded Core DFT Summary 5.28 Recommended Reading About the CD Glossary of Terms Index About the Author
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