注冊(cè) | 登錄讀書好,好讀書,讀好書!
讀書網(wǎng)-DuShu.com
當(dāng)前位置: 首頁出版圖書科學(xué)技術(shù)工業(yè)技術(shù)無線電電子學(xué)、電信技術(shù)基于Proteus的數(shù)字電路分析與設(shè)計(jì)

基于Proteus的數(shù)字電路分析與設(shè)計(jì)

基于Proteus的數(shù)字電路分析與設(shè)計(jì)

定 價(jià):¥35.00

作 者: 朱清慧,李定珍,尉喬南 等 編
出版社: 西安電子科技大學(xué)出版社
叢編項(xiàng): 高等學(xué)校應(yīng)用型本科“十三五”規(guī)劃教材
標(biāo) 簽: 暫缺

ISBN: 9787560642116 出版時(shí)間: 2016-09-01 包裝: 平裝
開本: 16開 頁數(shù): 300 字?jǐn)?shù):  

內(nèi)容簡(jiǎn)介

  《基于Proteus的數(shù)字電路分析與設(shè)計(jì)》圖文并茂、深入淺出地介紹了數(shù)字電路的有關(guān)知識(shí)?!痘赑roteus的數(shù)字電路分析與設(shè)計(jì)》共分為9章,第1~4章為基礎(chǔ)知識(shí)部分,主要介紹數(shù)字系統(tǒng)的概念、數(shù)制與碼制、門電路以及組合邏輯代數(shù);第5章為組合邏輯電路分析與設(shè)計(jì),以Proteus為平臺(tái),以實(shí)際器件應(yīng)用電路為載體進(jìn)行電路分析;第6章和第7章分別為鎖存器和觸發(fā)器、時(shí)序邏輯電路的分析與設(shè)計(jì),同樣以Proteus為平臺(tái),介紹實(shí)際器件應(yīng)用案例;第8章為脈沖波形發(fā)生器,介紹數(shù)字電路時(shí)鐘波形的產(chǎn)生以及波形的整形;第9章介紹了模一數(shù)和數(shù)一模轉(zhuǎn)換器。《基于Proteus的數(shù)字電路分析與設(shè)計(jì)》可作為應(yīng)用型本科院校計(jì)算機(jī)、機(jī)械、電子類等專業(yè)學(xué)生的數(shù)字電子技術(shù)基礎(chǔ)教程,也可作為教師的教學(xué)參考用書,同時(shí)也可供從事電子線路設(shè)計(jì)的工程技術(shù)人員學(xué)習(xí)和參考。

作者簡(jiǎn)介

暫缺《基于Proteus的數(shù)字電路分析與設(shè)計(jì)》作者簡(jiǎn)介

圖書目錄

第1章 數(shù)字系統(tǒng)的概念(Concept of Digital System)
1.0 概述(Introduction)
1.1 數(shù)字量和模擬量(Digital Quantity and Analog Quantity)
1.1.1 模擬量和模擬電信號(hào)(Analog Quantity and Analog Signal)
1.1.2 數(shù)字量和數(shù)字電信號(hào)(Digital Quantity and Digital Signal)
1.2 二進(jìn)制數(shù)、邏輯電平和數(shù)字波形(Binary Numbers,Logic Levels and Digital Waveforms)
1.2.1 二進(jìn)制數(shù)(Binary Numbers)
1.2.2 邏輯電平(Logic Levels)
1.2.3 數(shù)字波形(Digital Waveforms)
1.3 數(shù)據(jù)傳輸(Data Transmission)
1.4 基本邏輯運(yùn)算(Basic Logic Operation)
1.5 基本邏輯功能(Basic Logic Function)
1.5.1 比較功能(Comparison Function)
1.5.2 算術(shù)功能(Arithmetic Function)
1.6 數(shù)字集成電路(Digital Integrated Circuit)
1.6.1 集成芯片封裝(IC Package)
1.6.2 管腳序號(hào)(Pin Numbering)
1.6.3 集成電路分類(Integrated Circuit Classification)
1.6.4 集成電路技術(shù)(Integrated Circuit Technology)
第2章 數(shù)制與碼制(The Numeration System and Code System)
2.0 概述(Introduction)
2.1 十進(jìn)制數(shù)(Decimal Numbers)
2.2 二進(jìn)制數(shù)(Binary Numbers)
2.2.1 二進(jìn)制的表示方式(Binary Representations)
2.2.2 二進(jìn)制的優(yōu)點(diǎn)(Advantages of Binary)
2.2.3 二進(jìn)制的波形圖(Binary Waveform)
2.3 十進(jìn)制一二進(jìn)制轉(zhuǎn)換(Decimal to Binary Conversion)
2.3.1 整數(shù)部分(Integral Part)
2.3.2 小數(shù)部分(Decimal Part)
2.4 十進(jìn)制算術(shù)運(yùn)算(Binary Arithmetic Operation)
2.4.1 二進(jìn)制加法(Binary Addition)
2.4.2 二進(jìn)制減法(Binary Subtraction)
2.4.3 二進(jìn)制乘法和除法(Binary Multiplication and Division)
2.5 二進(jìn)制數(shù)的反碼和補(bǔ)碼(One's Complement and Two's Complement of Binary Numbers)
2.5.1 有符號(hào)數(shù)(Signed Numbers)
2.5.2 反碼和補(bǔ)碼(One's Complement and Two's Complement)
2.5.3 補(bǔ)碼的運(yùn)算(Operation of Two's Complement)
2.5.4 溢出(Overflow)
2.6 八進(jìn)制數(shù)(Octal Numbers)
2.6.1 八進(jìn)制數(shù)的表示方法(Representation of Octal Numbers)
2.6.2 八進(jìn)制數(shù)與二進(jìn)制數(shù)、十進(jìn)制數(shù)之間的轉(zhuǎn)換(Conversion of Octal Numbers into Binary Numbers&Conversion of 0ctal Numbers into Decimal Numbers)
2.7 十六進(jìn)制數(shù)(Hexadecimal Numbers)
2.7.1 十六進(jìn)制數(shù)的表示方法(Representation of Hexadecimal Numbers)
2.7.2 十六進(jìn)制數(shù)與二進(jìn)制數(shù)、十進(jìn)制數(shù)之間的轉(zhuǎn)換(Conversion of Hexadecimal Numbers into Binary Numbers&Conversion of Hexadecimal Numbers into Decimal Numbers)
2.8 BCD碼(Binary-Coded Decimal)
2.9 格雷碼和ASCII碼(Gray Code and ASCII Code)
2.9.1 格雷碼(Gray Code)
2.9.2 ASCII碼(ASCII Code)
習(xí)題(Exercises)
第3章 門電路(Gate Circuit)
3.0 概述(Introduction)
3.1 三極管的基本開關(guān)電路(Basic Switching Circuit of Triode)
3.1.1 雙極型三極管的基本開關(guān)電路(Basic Switching Circuit of BJT)
3.1.2 MOSFET基本開關(guān)電路(MOSFET Basic Switching Circuit)
3.1.3 TTL和CMOS的邏輯電平標(biāo)準(zhǔn)(Standard of TTL&CMOS Logic Levels)
3.2 TTL門電路的工作原理(Working Principle of TTL Gate Circuit)
3.2.1 TTL反相器(TTL Inverter)
3.2.2 TTL與非門(TTL AND-NOT Gate)
3.2.3 其它TTL門電路(Other TTL Gate Circuits)
3.3 CMOS門電路(CMOS Gate Circuit)
3.3.1 CMOS基本邏輯門電路(CMOS Basic Logic Gate Circuit)
3.3.2 帶緩沖器的CMOS門電路(CMoS Gate Circuit with Buffer)
3.4 其它功能門電路(Gate Circuits of Other Functions)
3.4.1 CMOS傳輸門(CMOS Transmission Gate)
3.4.2 三態(tài)門(Three-state Gate)
3.4.3 集電極開路門(Open Collector Gate)
3.5 數(shù)字集成芯片實(shí)用常識(shí)(Practical Common Sense of Digital Integrated Chip)
3.5.1 數(shù)字集成芯片分類及命名(Classification and Nomenclature of Digital Integrated Chip)
3.5.2 數(shù)字集成芯片管腳的處理(Processing of Digital Integrated Chip Pin)
習(xí)題(Exercises)
第4章 組合邏輯代數(shù)(Combined Logic Algebra)
4.0 概述(Introduction)
4.1 布爾運(yùn)算的定律和法則(Laws and Rules of Boolean Operation)
4.1.1 基本公式(Basic Formulas)
4.1.2 常用公式(Common Formulas)
4.1.3 邏輯代數(shù)的基本定理(Fundamental Theorem of Logical Algebra)
4.2 邏輯函數(shù)及其表示方法(Logic Function&It's Representation)
4.2.1 邏輯函數(shù)(Logic Function)
4.2.2 邏輯函數(shù)的表示方法(Representation of Logic Function)
4.2.3 邏輯函數(shù)形式的轉(zhuǎn)換(Conversion of Logic Function Forms)
4.2.4 標(biāo)準(zhǔn)與或式和標(biāo)準(zhǔn)或與式(Standard AND-OR Form&Standard OR-AND Form)
4.2.5 邏輯函數(shù)形式的變換(Variation of Logic Function Forms)
4.3 邏輯函數(shù)的化簡(jiǎn)方法(Approaches of Logic Function Simplification)
4.3.1 公式法化簡(jiǎn)(Simplifying Logic Algebra through Laws and Rules)
4.3.2 卡諾圖法化簡(jiǎn)(Simplifying Logic Algebra through Karnaugh Maps)
4.4 具有約束的邏輯函數(shù)的化簡(jiǎn)(Simplification of Logic Function with Constraint)
4.4.1 約束項(xiàng)和約束條件(Constraint Term and Constraint Condition)
4.4.2 具有約束的邏輯函數(shù)的公式法化簡(jiǎn)(Simplification of Logic Function with Constraints through Laws and Rules)
4.4.3 具有約束的邏輯函數(shù)的卡諾圖法化簡(jiǎn)(Simplification of Logic Function with Constraints through Karnaugh Maps)
習(xí)題(Exercises)
第5章 組合邏輯電路分析與設(shè)計(jì)(Analysis and Design of Combinational Logic Circuit)
5.0 概述(Introduction)
5.1 組合邏輯電路的分析和設(shè)計(jì)方法(Analysis and Design Method of Combinational Logic Circuit)
5.1.1 組合邏輯電路的分析方法(Analysis Method of Combinational Logic Circuit)
5.1.2 組合邏輯電路的設(shè)計(jì)方法(Design Method of ComBinational Logic Circuit)
5.2 常用組合邏輯集成芯片(Common Combinational Logic Integrated Chip)
5.2.1 編碼器(Encoder)
5.2.2 譯碼器(Decoder)
5.2.3 數(shù)據(jù)分配器(Demultiplexer)
5.2.4 數(shù)據(jù)選擇器(Multiplexer)
5.2.5 加法器(Adder)
5.2.6 全減器(Full Subtractor)
5.2.7 數(shù)據(jù)比較器(Data Comparator)
5.3 組合邏輯電路中的競(jìng)爭(zhēng)和冒險(xiǎn)(Competition and Adventure in Combinationa Logical Circuit)
5.3.1 產(chǎn)生競(jìng)爭(zhēng)和冒險(xiǎn)的原因(Causes of Competition and Adventure)
5.3.2 消除競(jìng)爭(zhēng)和冒險(xiǎn)的方法(Methods of Clearing Competition and Adventure)
5.4 總結(jié)(Summary)
習(xí)題(Exercises)
第6章 鎖存器和觸發(fā)器(Latchs and Flip-Flops)
6.0 概述(Introduction)
6.1 SR鎖存器(SR Latch)
6.1.1 低電平輸入有效的SR鎖存器(SR Latch with Low Active Input Level)
6.1.2 高電平輸入有效的SR鎖存器(SR Latch with High Active Input Level)
6.1.3 SR鎖存器的應(yīng)用(Application of SR Latch)
6.2 觸發(fā)器(Flip-Flops)
6.2.1 電平觸發(fā)的觸發(fā)器(Level Triggered Flip-Flops)
6.2.2 脈沖觸發(fā)的觸發(fā)器(Pulse Triggered Flip-Flops)
6.2.3 邊沿觸發(fā)的觸發(fā)器(Edge Triggered Flip-Flops)
6.2.4 觸發(fā)器功能匯總(Function Summary of Flip-Flops)
6.3 總結(jié)(Summary)
習(xí)題(Exercises)
第7章 時(shí)序邏輯電路的分析與設(shè)計(jì)(Analysis and Design of Sequential Logic Circuit)
7.0 概述(Introduction)
7.1 時(shí)序邏輯電路的分析方法(Analysis Methods of Sequential Logic Circuit)
7.1.1 同步時(shí)序邏輯電路的分析方法(Analysis Methods of Synchronous Sequential Logic Circuit)
7.1.2 異步時(shí)序邏輯電路的分析方法(Analysis Methods of Asynchronous Sequential Logic Circuit)
7.2 計(jì)數(shù)器(Counters)
7.2.1 異步計(jì)數(shù)器(Asynchronous Counter)
7.2.2 同步計(jì)數(shù)器(Synchronous Counter)
7.2.3 an/減計(jì)數(shù)器(Up/Down Counter)
7.2.4 任意進(jìn)制計(jì)數(shù)器的集成芯片連接(Connection of Module-N Counter with Integrated Chip)
7.3 寄存器和移位寄存器(Register and Shift Register)
7.3.1 寄存器(Register)
7.3.2 移位寄存器(Shift Register)
7.4 環(huán)形計(jì)數(shù)器和扭環(huán)形計(jì)數(shù)器(Ring Counter and Twisted-Ring Counter)
7.4.1 環(huán)形計(jì)數(shù)器(Ring Counter)
7.4.2 扭環(huán)形計(jì)數(shù)器(Twisted-Ring Counter)
7.5 時(shí)序邏輯電路的設(shè)計(jì)方法(Design Methods of Sequential Logic Circuit)
7.5.1 順序脈沖發(fā)生器的設(shè)計(jì)(Design of Sequence Pulse Generator)
7.5.2 序列信號(hào)發(fā)生器的設(shè)計(jì)(Design of Sequence Signal Generator)
7.5.3 同步時(shí)序邏輯電路的設(shè)計(jì)方法(Design Methods of Synchronous Sequential Logic Circuit)
7.5.4 異步時(shí)序邏輯電路的設(shè)計(jì)方法(Design Methods of Asynchronous Sequential Logic Circuit)
7.6 總結(jié)(Summary)
習(xí)題(Exercises)
第8章 脈沖波形發(fā)生器(Pulse Waveform Generator)
8.0 概述(Introduction)
8.1 施密特觸發(fā)器(Schmitt Trigger)
8.1.1 門電路組成的施密特觸發(fā)器(Schmitt Trigger with Gate Circuit)
8.1.2 CMOS集成施密特觸發(fā)器(Integrated Schmitt Trigger with CMOS)
8.1.3 施密特觸發(fā)器的應(yīng)用(Application of Schmitt Trigger)
8.2 555定時(shí)器(555 Timer)
8.2.1 555定時(shí)器的工作原理(Working Principle of 555 Timer)
8.2.2 用555定時(shí)器構(gòu)成的多諧振蕩器(Multi-Vibrator with 555 Timer)
8.2.3 用555定時(shí)器構(gòu)成的單穩(wěn)態(tài)觸發(fā)器(Mono-Stable Stable Trigger with 555 Tliner)
8.2.4 用555定時(shí)器構(gòu)成的施密特觸發(fā)器(Schmitt Trigger with of 555 Timer)
8.3 集成單穩(wěn)態(tài)觸發(fā)器(Integrated Mono-Stable Trigger)
8.3.1 用CMOS門電路組成的微分型單穩(wěn)態(tài)觸發(fā)器(Differential Mono-Stable Trigger Composed of CMOS Gate Circuit)
8.3.2 集成單穩(wěn)態(tài)觸發(fā)器(Integrated Mono-Stable Multi-Vibrator)
習(xí)題(Exercises)
第9章 模-數(shù)和數(shù)-模轉(zhuǎn)換器(Analog to Digital and Digital to Analog Converters)
9.0 概述(Introduction)
9.1 A/D轉(zhuǎn)換器(Analog to Digital Convertors)
9.1.1 A/D轉(zhuǎn)換器的基本原理(Basic Principle of A/D Converter)
9.1.2 A/D轉(zhuǎn)換器精度與轉(zhuǎn)換速度(Precision and Speed of A/D Converter)
9.2 A/D轉(zhuǎn)換器的應(yīng)用與仿真(Application and Simulation of A/D Converter)
9.2.1 八位單極性并行輸出ADC0808(ADC0808 with Unipolar Voltage Input and Parallel Output of Eight Bits)
9.2.2 雙通道串行輸出ADC0832(ADC0832 with Dual Channels Input and Serial Output)
9.2.3 雙極性A/D轉(zhuǎn)換器(A/D Converter with Bipolar Voltage Input)
9.3 D/A轉(zhuǎn)換器(Digital to Analog Converter)
9.3.1 權(quán)電阻網(wǎng)絡(luò)D/A轉(zhuǎn)換器(D/A Converter with Weight Resistance Network)
9.3.2 倒T型電阻網(wǎng)絡(luò)D/A轉(zhuǎn)換器(D/A Converter with Inverted T Type Resistor Network)
9.3.3 權(quán)電流型D/A轉(zhuǎn)換器(D/A Converter with Power Current Mode)
9.3.4 D/A轉(zhuǎn)換器的轉(zhuǎn)換精度(Conversion Accuracy of D/A Converter)
9.4 D/A轉(zhuǎn)換器的應(yīng)用與仿真(Application and Simulation of D/A Converter)
9.4.1 DAC0832
9.4.2 DAC0808
習(xí)題(Exercises)
參考文獻(xiàn)

本目錄推薦

掃描二維碼
Copyright ? 讀書網(wǎng) ranfinancial.com 2005-2020, All Rights Reserved.
鄂ICP備15019699號(hào) 鄂公網(wǎng)安備 42010302001612號(hào)